This invention relates generally to electronic memory, and more particularly to methods and circuits for writing write-once read-many (WORM) memory devices.
In the field of memories, there is a demand for ever increasing densities and lower cost. This is especially true for non-volatile memories, i.e., those that do not lose data when power is not supplied. A non-volatile memory may be write-once-read-many (xe2x80x9cWORMxe2x80x9d) or reprogrammable. As the name suggests, a WORM memory is written (programmed) once, and it is thereafter permanent for all practical purposes. Most WORM memories are field programmable, rather than requiring that programming be performed during manufacture. Examples of field programmable WORM memories include bipolar PROM (programmable read only memory), CMOS (complementary metal oxide semiconductor) PROM, EPROM (erasable PROM), and tunnel-junction based ROM.
WORM memories are programmed by applying a relatively large voltage to selected cells in order to alter the physical characteristics of the selected cells. The alteration mechanism depends upon the type of memory. For instance, a unit memory cell of a bipolar or CMOS PROM typically consists of one transistor in series with a fuse and/or an anti-fuse, and a PROM is programmed by applying a large voltage across the fuse or anti-fuse of the selected cells. The applied voltage causes the fuse to open or the anti-fuse to short (or both if both are present). As a result, the resistance across the cell is altered, and a reading operation can detect the alteration, as contrasted with the unaltered state, by applying a small read voltage to the cell and sensing the current flowing through the cell. As another example, a unit memory cell of a EPROM typically consists of a transistor and a floating gate, and an EPROM is programmed by applying a large potential to transfer charge from the silicon substrate to the floating gate of selected cells. The mechanism for the charge transfer in this case is Fowler-Nordheim electron tunneling.
Another example of a memory cell is an anti-fuse tunnel junction 100, which is illustrated in FIG. 1. The anti-fuse tunnel junction 100 includes abottom electrode 120, and insulator barrier layer 140 and a top electrode 160. The bottom electrode 120 and the top electrode 160 could be conductor metals such as Cu, Al or the like or magnetic materials such as NiFe, CoFe, NiFeCo or the like. The insulator barrier layer 140 is typically very thin, from 5 xc3x85 (Angstroms) to 100 xc3x85. Generally, the insulator barrier layer 140 is made of TaOx, AlOx, SiOx, SiNx, AlNx or the like. As a bias voltage is applied across the junction, the thin insulator barrier allows quantum mechanical tunneling to occur and a current flows from one electrode, across the barrier layer 140, to the other electrode. The resistance of the tunnel junction is exponentially dependent on the thickness of the barrier layer. Therefore, by controlling the thickness during manufacturing, the tunnel junction can be made to a desired resistance value that is suitable for a particular application.
A circuit for programming a generic WORM memory is part of a WORM memory system 200 illustrated in FIG. 2A. The WORM memory system 200 comprises an array of memory cells 210. The memory cells 210 are preferably set in a rectangular arrangement of rows and columns. Each memory cell 210 is at the intersection of row conductor 220 and a column conductor 230. A row decoder 240 connects to the row conductors 220, and a column decoder 250 connects to the column conductors 230. Address lines (not shown) control the row decoder 240 and/or the column decoder 250 to select a desired row, column or individual cell 210. As illustrated in FIG. 2A, one particular cell 210 has been selected for writing. As part of the writing process, a write voltage VWR is applied across the cell 210.
A graph 260 of the write voltage VWR is illustrated in FIG. 2B. The write voltage VWR is a pulse 270 of height V1 and fixed width T1. For every cell 210 to be written, that cell 210 is selected through the row decoder 240 and the column decoder 250; then, the same pulse 270 is applied to the selected cell(s).
A disadvantage of WORM memories is that V1 is typically required to be a high value to program the memories. In the case of an EPROM, a high voltage is needed for Fowler-Nordheim electron tunneling to occur. In the case of PROM with a polysilicon fuse as the programmable element, a large voltage is needed to deliver enough energy to blow the polysilicon fuse. In the case of a bipolar PROM with one forward and one reversed diode as a memory cell, a large voltage is needed to exceed the reverse voltage of the diode to cause it to breakdown. In the case of a WORM with a tunnel junction anti-fuse as a programmable element, the breakdown voltage of the tunnel junction is as low as 1.5 V (volts). This breakdown voltage can be controlled by the thickness of the barrier layer of the tunnel junction. A thicker barrier has a higher breakdown voltage, and a thinner barrier has a lower breakdown voltage, but these types of anti-fuse junctions exhibit significant variations in breakdown voltage.
The programming of some WORM memories exhibit significant variability from cell to cell in the required writing voltage level. This variation can result from physical variation from cell to cell in the manufacturing process. Some cells may require less energy to be programmed, while other cells may require more. In other words, the pulse 270 may be longer than necessary for some cells yet too short for other cells. To increase yield rates, the pulse duration T, is typically much longer than necessary for the vast majority of cells.
It is known in the art to verify the efficacy of a writing operation and to repeat the standard writing operation when it has been unsuccessfully attempted. Typically, the efficacy of a writing operation is tested by sensing the output voltage from a sense amplifier (not shown) connected to the output of the memory cell 210. An example of such an approach is disclosed in U.S. Pat. No. 5,684,741.
In one respect, the invention is a method for writing a memory cell. The method applies a pulse train to a write line connected to the memory cell. The number of pulses in the pulse train is not predetermined. The method compares a value on an input side of the cell to a reference value, wherein the input side of the memory cell provides an indication that a writing operation is complete. The method discontinues the pulse train on the write line, in response to the comparing step, preferably if the value on the write line exceeds the reference value. Preferably, the pulses are short in width and large in magnitude. The method may optionally count the number of pulses in the pulse train, and discontinue the pulse train on the write line and/or declare the cell as unusable if the number of pulses exceeds a predetermined maximum.
In another respect, the invention is a circuit for writing a memory cell. The circuit comprises a pulse train generator and a comparator. The pulse train generator has an output and an enable input. The output is connected to a write line connected to the memory cell. The output, when enabled, carries a pulse train. The comparator has two inputs and an output. One of the inputs is connected to the write line. The other of the inputs is connected to a reference. The comparator output is connected to the enable input of the pulse train generator, whereby the pulse train generator is disabled or enabled depending upon the comparator output. Optionally, the circuit further comprises a counter that counts pulses and disables the pulse train generator after a predetermined maximum number of pulses.
In yet another respect, the invention is a memory system. The memory system comprises an array of memory cells, a write line, and a pulse train generator and comparator as described above.
As used herein, the terms xe2x80x9chas,xe2x80x9d xe2x80x9chavexe2x80x9d and xe2x80x9chavingxe2x80x9d are open-ended. Thus, for example, the pulse train generator may comprise other signal interfaces besides the output and the enable input referred to above. Furthermore, the terms xe2x80x9cconnectedxe2x80x9d and its variants, as used herein, mean connected directly or indirectly through an intermediary element.
In comparison to known prior art, certain embodiments of the invention are capable of achieving certain advantages, including some or all of the following: (1) the writing process is faster and more reliable; (2) elements in series with the memory cell are less likely to be damaged; (3) the writing process utilizes less power; (4) the number of pulses necessary can be calibrated in advance; (5) the number of pulses required for writing is a measure of the quality of the memory cell; and (6) no cross connections from the array outputs are needed, as all relevant circuitry is on only the writing side of the array. Those skilled in the art will appreciate these and other advantages and benefits of various embodiments of the invention upon reading the following detailed description of a preferred embodiment with reference to the below-listed drawings.